Semiconductor Memory Device

ABSTRACT

Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal (in the case shown in FIG.  1 , an external upper limit fetch signal) is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a Divisional Application, which claims the benefit of pendingU.S. patent application Ser. No. 11/102,715, filed Apr. 11, 2005. Thedisclosure of the prior application is hereby incorporated herein in itsentirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device, andparticularly to a semiconductor memory device having an error correctionfunction.

2. Description of the Related Art

In a semiconductor memory device such as a DRAM (Dynamic Random AccessMemory) mounted on computer equipments, a necessary memory capacityrapidly increases in recent years. In response to the increase in memorycapacity, a miniaturization technique progresses. However, when theminiaturization technique progresses, reliability in a memory cell isreduced. In order to prevent the reduction in reliability, the followingredundant technique has been used. An extra memory region (redundantregion) is provided in a memory cell array. In place of a defectivememory cell in a normal memory cell array region, a non-defective memorycell in the redundant region is selected to relieve defects. Accordingto this technique, although the reduction in the reliability of productsthemselves can be prevented, the following problem occurs in recentyears. In the memory cell requiring a refresh operation, such as a DRAMcell, a data retention time is suddenly degraded, and thereby defectsoccur after packaging or shipping of products.

One example of countermeasures for the defects caused by data retentiontime degradation includes a method of mounting an ECC (Error Checkingand Correcting) function. In the method of mounting a commonly used ECCfunction capable of 1-bit error correction, even when read-out data havean error of 1-bit, the error can be corrected using the ECC function.Further, a method of mounting the ECC function to allow it to take overthe repair of defects by the redundant technique is also considered.More specifically, when the error within the ECC code (e.g., hammingcode) is a 1-bit error, the error correction is performed by eachread-out operation in a state of a 1-bit error without using theredundant region.

Therefore, a single-bit defect (it means a defect that not two or moredefects but only one defect is generated by one read-out operation dueto BL (bit line) short/open) to some extent can be repaired withoutusing the redundant region. As a result, even defective chips which areheretofore discarded due to excessive amounts of defective bits thatcannot be repaired using a predetermined redundant region can be changedinto non-defective chips. Therefore, this can contribute to improvementin the yield.

However, when the number of single-bit defects of which the repair bythe redundant technique can be taken over by the ECC function is toolarge, a probability of repair defective bits caused by a data retentiontime degradation is reduced. Accordingly, what becomes important here isas follows. The first point is that the number of defective bits ofwhich the repair by the redundant technique can be taken over by the ECCfunction is determined at the time of packaging or shipping chips asproducts. The second point is that the test operation can be performed.

For that purpose, a semiconductor memory device having a counter, aregister, a comparison circuit, and an output circuit is required. Eachelement has the following function. The counter can count the number oferror corrections. The register can set the upper limit of the number oferror corrections. The comparison circuit can compare values of thecounter with those of the register. The output circuit can output thecomparison results.

The semiconductor memory device having the above-described functions isdisclosed, for example, in Japanese Unexamined Patent Publication No.49-60450 (p. 3, FIG. 2), Japanese Unexamined Patent Publication No.1-94599 (pp. 4-5, FIG. 1), and Japanese Unexamined Patent PublicationNo. 6-131884 (paragraph numbers [0006] to [0008], and FIG. 1). Thesemiconductor memory device has the following configuration.

FIG. 9 shows a configuration of a conventional semiconductor memorydevice.

A conventional semiconductor memory device 20 has a data bit section 21,a parity bit section 22, an error correction circuit 23, a paritycalculation circuit 24, a counter 25, a register 26, a comparisoncircuit 27, an output circuit 28 and an input circuit 29. The data bitsection 21 stores a data bit out of data stored in a memory cell arraycomprised of memory cores (not shown). The parity bit section 22 storesa parity bit out of data stored in a memory cell array comprised ofmemory cores (not shown). The error correction circuit 23 performs anerror correction with reference to the data bit and the parity bit. Theparity calculation circuit 24 generates a parity bit according to inputdata, for example, by the operation based on a hamming code. The counter25 counts the number of error corrections. The register 26 stores anupper limit of the number of error corrections. The comparison circuit27 compares the counted number of error corrections with the upper limitof the number of error corrections stored in the register 26.

In the conventional semiconductor memory device 20, the error correctioncircuit 23 performs a 1-bit error detection and a 1-bit error correctionwith reference to, for example, 64 data bits and 7 parity bits. Whendetecting a defective bit, the circuit 23 inverts the bit for the errorcorrection and then, outputs the results through the output circuit 28.The counter 25 counts the number of error corrections when a count startsignal is inputted during the test operation. The comparison circuit 27compares the number of error corrections with the upper limit of thenumber of error corrections previously stored in the register 26, andthereby judging whether or not the number of error corrections exceeds apredetermined upper limit. When the number of error corrections exceedsthe upper limit, the output circuit 28 generates an alarm.

The conventional semiconductor memory device, however, has some problemsas described hereinbelow. The first problem is as follows. Even if thenumber of error corrections counted during the test operation is toolarge or too small with respect to the set upper limit, the upper limitcannot be arbitrarily set. This upper limit is an upper limit of thenumber of the defective bits of which the repair by the redundanttechnique can be taken over by the ECC function. Accordingly, defectivebits beyond the upper limit are repaired by the redundant region.Therefore, the second problem is as follows. When the upper limit is toosmall, many redundant regions are required depending on the number oferror corrections. On the contrary, when the upper limit is too large, aprobability of relieving the defective bits caused by a data retentiontime degradation is reduced in the case where the number of errorcorrections is large.

The third problem is as follows. Due to deterioration with time of thememory cell, the number of the defective bits after the packaging orshipping increases more than that during the test operation in somecases. Despite this, there is no section for grasping this situation.

The fourth problem is as follows. Depending on the test pattern, thesame address data are accessed two or more times in some cases and atthis time, the defective bit is carelessly counted two or more times.

SUMMARY OF THE INVENTION

In view of the foregoing, it is an object of the present invention toprovide a semiconductor memory device capable of arbitrarily setting anupper limit of the number of error corrections during a test operation.

It is another object of the present invention to provide a semiconductormemory device capable of grasping an increase of defective bits due todeterioration with time of a memory cell.

It is yet another object of the present invention to provide asemiconductor memory device capable of correctly counting the number oferror corrections.

To accomplish the above-described objects, according to one aspect ofthe present invention, there is provided a semiconductor memory devicehaving an error correction function that corrects a defective bit. Thissemiconductor memory device comprises the following elements: a counterthat counts the number of error corrections; an upper limit settingsection that changes an upper limit of the number of error correctionsin response to an upper limit setting signal inputted externally; and acomparator that compares the number of error corrections with the upperlimit.

According to another aspect of the present invention, there is provideda semiconductor memory device having an error correction function thatcorrects a defective bit. This semiconductor memory device comprises thefollowing elements: a counter that counts the number of errorcorrections; an upper limit setting section that, when an upper limitsetting signal is inputted externally, sets a count result of the numberof error corrections in the counter as an upper limit of the number oferror corrections; and a comparator that compares the upper limit withthe count result in the counter after the passing of a predeterminedtime.

According to yet another aspect of the present invention, there isprovided a semiconductor memory device having an error correctionfunction that corrects a defective bit. This semiconductor memory devicecomprises the following elements: a counter that counts the number oferror corrections; an upper limit setting section that stores an upperlimit of the number of error corrections and that, when an upper limitsetting signal is externally inputted after completion of the countingin the counter, increments or decrements the upper limit insynchronization with a clock signal; and a comparator that compares acount result in the counter with the upper limit.

According to yet another aspect of the present invention, there isprovided a semiconductor memory device having an error correctionfunction that corrects a defective bit. This semiconductor memory devicecomprises the following element: an error correction memory section thatstores error correction information of whether or not the errorcorrection is performed, at every combination of data bits and paritybits required to construct a code capable of 1-bit error correction.

The above and other objects, features and advantages of the presentinvention will become apparent from the following description when takenin conjunction with the accompanying drawings which illustrate preferredembodiments of the present invention by way of example.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a configuration of a semiconductor memory device accordingto a first embodiment of the present invention.

FIG. 2 shows a configuration of a semiconductor memory device accordingto a second embodiment of the present invention.

FIG. 3 shows a configuration of a semiconductor memory device accordingto a third embodiment of the present invention.

FIG. 4 shows a configuration of a semiconductor memory device accordingto a fourth embodiment of the present invention.

FIG. 5 is a timing chart showing a state of writing of error correctioninformation into an error correction memory bit.

FIG. 6 shows a storage state of a memory core after the writing of errorcorrection information into an error correction memory bit.

FIG. 7 is a timing chart showing a state of read-out of an errorcorrection memory bit and a state of counting of the number of errorcorrections.

FIG. 8 shows a configuration of a semiconductor memory device accordingto a fifth embodiment of the present invention.

FIG. 9 shows a configuration of a conventional semiconductor memorydevice.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiment of the present invention will be described indetail below with reference to the accompanying drawings, wherein likereference numerals refer to like elements throughout.

FIG. 1 shows a configuration of a semiconductor memory device accordingto a first embodiment of the present invention.

The semiconductor memory device 10 a of the first embodiment has thefollowing elements: a data bit section 11 that stores a data bit; aparity bit section 12 that stores a parity bit; an error correctioncircuit 13 that performs an error correction with reference to the databit and the parity bit; a parity calculation circuit 14 that generates aparity bit in response to input data by the calculation based on, forexample, a hamming code; a counter 15 a that counts the number of errorcorrections; a register 16 a that sets an upper limit of the number oferror corrections; a comparison circuit 17 that compares the countednumber of error corrections with the upper limit of the number of errorcorrections stored in the register 16 a; an output circuit 18; and aninput circuit 19.

The data bit section 11 and the parity bit section 12 each areconfigured by memory cell arrays comprised of memory cores (not shown).The memory cell array is configured by a 4-bit or 8-bit unit such thatfour or eight memory cells are selected on one column selection line.

A sense amplifier, a write amplifier, or a column decoder or row decoderthat specifies an address is omitted in the figure.

In the semiconductor memory device 10 a of the first embodiment, theregister 16 a that stores the upper limit of the number of errorcorrections is different from that of a conventional semiconductormemory device. More specifically, the register 16 a changes the upperlimit in response to the upper limit setting signal (which ishereinafter referred to as an “external upper limit fetch signal” in thefirst embodiment) inputted externally. A setting upper limit is fetchedin the register 16 a through data input/output pins (not shown), forexample, when the external upper limit fetch signal goes to a high levelduring the test operation. The upper limit is an upper limit of thenumber of defective bits of which the repair by the redundant techniquecan be taken over by the ECC function.

Operations of the semiconductor memory device 10 a are described below.

At the time of data writing, data inputted from the data input/outputpins (not shown) are stored in a specified address in the data bitsection 11 through the input circuit 19. On this occasion, the paritycalculation circuit 14 generates a parity bit in response to input databy the calculation based on an ECC code (e.g., a hamming code). Then,the parity bit section 12 stores the generated parity bit in apredetermined address.

For example, when constructing the ECC code capable of 1-bit errorcorrection, the following parity bits each are generated. The paritybits of 4 bits, 5 bits, 7 bits and 8 bits are generated for the databits of 8 bits, 16 bits, 64 bits and 128 bits, respectively. Then, thegenerated parity bits are stored in the parity bit section 12.

On the other hand, at the time of data read-out operation, for example,the 64 data bits and 7 parity bits which are required to construct theECC code are read out in one read-out operation from the addressesspecified in the data bit section 11 and the parity bit section 12. Onthis occasion, the error correction circuit 13 performs a 1-bit errordetection and a 1-bit error correction with reference to the data bitsand the parity bits. When detecting a defective bit, the circuit 13inverts the bit for the error correction and outputs the corrected data.

Next, operations during the test are described.

During the test operation, addresses are incremented or decrementedaccording to a predetermined test pattern, so that all the address dataof the data bit section 11 and the parity bit section 12 are accessed.The error correction circuit 13 performs a 1-bit error detection and a1-bit error correction with reference to, for example, the 64 data bitsand the 7 parity bits corresponding thereto, which are required toconstruct the ECC code. The counter 15 a starts a counting operation ofthe number of error corrections when a count start signal inputted froman external pin goes to a high level during the test operation. At thistime, a count value outputted from the counter and the upper limit ofthe number of error corrections stored in the register 16 a are inputtedinto the comparison circuit 17 and compared. The comparison result inthe comparison circuit 17 is outputted through the output circuit 18.When the count value in the counter 15 a does not reach the upper limitset in the register 16 a, the counter 15 a continuously counts thenumber of error corrections. When the test using a predetermined testpattern is completed, for example, the count start signal inputted intothe counter 15 a goes to a low level and as a result, the counter 15 astops the counting operation of the number of error corrections.Further, when the count value in the counter 15 a reaches the upperlimit during the test operation, the output circuit 18 generates, forexample, an alarm and as a result, the counter 15 a stops the countingoperation.

Incidentally, this upper limit is an upper limit of the number ofdefective bits of which the repair by the redundant technique can betaken over by the ECC function. Therefore, when the upper limit is toosmall, many redundant regions are required depending on the number oferror corrections. On the contrary, when the upper limit is too large, aprobability of relieving the defective bits caused by a data retentiontime degradation is reduced in the case where the number of errorcorrections is large. Therefore, the semiconductor memory device 10 a ofthe first embodiment is configured such that the upper limit set in theregister 16 a can be adjusted during the test operation. Morespecifically, after completion of the counting of the number of errorcorrections, when the external upper limit fetch signal inputted goesto, for example, a high level, the register 16 a fetches the settingupper limit from the data input/output pins (not shown) and sets it as anew upper limit.

The register 16 a sets the upper limit, for example as follows. Aftercompletion of the counting of the number of error corrections, theregister 16 a changes the upper limit according to generation of analarm. Based on whether or not the generation of an alarm changes by thechange of the upper limit, the register 16 a detects the approximatenumber of error corrections. In addition, the defective bit caused bythe data retention time degradation is estimated. Thus, the upper limitis set. As a result, the upper limit can be set according to the numberof error corrections during the test.

Next, the semiconductor memory device of a second embodiment isdescribed.

FIG. 2 shows a configuration of the semiconductor memory deviceaccording to the second embodiment of the present invention.

In the diagram, the same elements as those in the semiconductor memorydevice 10 a of the first embodiment are indicated by the same referencenumerals as in the device 10 a and the description is omitted.

In the semiconductor memory device 10 b of the second embodiment, aregister 16 b that sets an upper limit is different from the register 16a in the semiconductor memory device 10 a of the first embodiment. Whenthe upper limit setting signal (referred to as a “count value memorysignal” in the second embodiment) is inputted (goes to a high level)externally, the register 16 b sets a count result of the number of errorcorrections in the counter 15 a as the upper limit of the number oferror corrections.

Operations of the semiconductor memory device 10 b of the secondembodiment are described below. Operations during the reading and thewriting are the same as those in the semiconductor memory device 10 a ofthe first embodiment and the description is omitted.

During the test operation, after completion of counting of the number oferror corrections by the counter 15 a, when the count value memorysignal goes to, for example, a high level, the register 16 b stores thecount result. After passing of a predetermined time in which a stresstest is performed, a test is performed again by using the same testpattern as that used in a previous test. The comparison circuit 17compares the previous count result which is set in the register 16 bwith this count result which is outputted from the counter 15 a. Whenthis count result increases more than the previous one, the outputcircuit 18 generates, for example, an alarm. Therefore, deteriorationwith time can be grasped.

In addition, the semiconductor memory device 10 a of the firstembodiment may be configured as follows. The count value memory signalis allowed to be inputted into the register 16 a. When the signal goesto a high level, the register 16 a stores the count value in the counter15 a instead of fetching the upper limit externally.

Next, a semiconductor memory device of a third embodiment is described.

FIG. 3 shows a configuration of the semiconductor memory deviceaccording to the third embodiment of the present invention.

In the diagram, the same elements as those in the semiconductor memorydevices 10 a and 10 b of the first and second embodiments are indicatedby the same reference numerals as those in the devices 10 a and 10 b andthe description is omitted.

In the semiconductor memory device 10 c of the third embodiment, theregister 16 c is different from the register 16 a in the semiconductormemory device 10 a of the first embodiment. When the upper limit settingsignal (referred to as an “upper limit increment/decrement signal” inthe third embodiment) is externally inputted (goes to a high level), theregister 16 c increments or decrements the upper limit insynchronization with a clock signal.

Operations of the semiconductor memory device 10 c of the thirdembodiment are described below. Operations during the reading and thewriting are the same as those in the semiconductor memory devices 10 aand 10 b of the first and second embodiments and the description isomitted.

During the test operation, after completion of counting of the number oferror corrections by the counter 15 a, when the upper limitincrement/decrement signal goes to, for example, a high level, theregister 16 c increments or decrements the previously stored upper limitin synchronization with a clock signal. On each occasion, the comparisoncircuit 17 compares the count result of the number of error correctionswith the upper limit. For example, when no alarm is generated, the upperlimit is decremented. By doing so, the upper limit is made smaller thanthe count result of the number of error corrections on reaching acertain value. As a result, an alarm is generated. On the other hand,when an alarm is generated, the upper limit is incremented. By doing so,the upper limit exceeds the count result of the number of errorcorrections on reaching a certain value. As a result, no alarm isgenerated. That is, details of the number of error corrections can begrasped based on the signal outputted from the comparison circuit 17.

In addition, the semiconductor memory device 10 a of the firstembodiment may be configured as follows. After completion of thecounting of the number of error corrections by the counter 15 a, theupper limit increment/decrement signal is inputted to the register 16 a,so that the details of the number of error corrections may be grasped.

Next, a semiconductor memory device of a fourth embodiment is described.

FIG. 4 shows a configuration of the semiconductor memory device of thefourth embodiment.

In the diagram, the same elements as those in the semiconductor memorydevices 10 a, 10 b and 10 c of the first to third embodiments areindicated by the same reference numerals as those in the devices 10 a,10 b and 10 c and the description is omitted.

The semiconductor memory device 10 d of the fourth embodiment has thefollowing function. When performing a test using a test pattern that thesame address data are accessed two or more times, a defective bit isprevented from being counted two or more times. In order to realize thefunction, the semiconductor memory device 10 d has an error correctionmemory bit 12 a. The bit 12 a stores error correction information ofwhether or not an error correction is performed, at every combination ofthe data bits and parity bits which are required to construct the ECCcode (e.g., a hamming code) capable of 1-bit error correction. A counter15 b, when a count start signal is inputted, counts the number of errorcorrections based on the error correction information stored in theerror correction memory bit 12 a.

The memory cell array is generally configured by a 4-bit or 8-bit unit.That is, four or eight memory cells are selected on one column selectionline. For example, in the case where the array is configured by a 8-bitunit, when the hamming code is constructed using 7 parity bits to 64data bits, a surplus of 1 bit occurs because 7 bits are required for thestorage of the parity bits.

Consequently, the surplus of 1 bit is allocated to the error correctionmemory bit 12 a, so that the function can be realized without increaseof the memory cell array.

Operations of the semiconductor memory device 10 d of the fourthembodiment are described below.

Operations during the reading and the writing are the same as those inthe semiconductor memory devices 10 a, 10 b and 10 c of the first tothird embodiments and the description is omitted.

During the test operation, the semiconductor memory device 10 d firstaccesses all the address data of a memory cell array and then performs1-bit error detection and 1-bit error correction using the errorcorrection circuit 13.

FIG. 5 is a timing chart showing a state of writing of error correctioninformation into an error correction memory bit.

Herein, an address Add (0) is first selected. Then, a read-out operationfrom the memory core (Core) is performed, for example, at everycombination of 64 data bits and 7 parity bits, whereby 1-bit errordetection and 1-bit error correction are performed by the errorcorrection circuit 13. The result is written, as the error correctioninformation, into the error correction memory bit 12 a of the memorycore. For example, when the error correction is performed, “1” is storedin the memory bit 12 a, and when the error correction is not performed,“0” is stored in the memory bit 12 a. When performing theabove-described processing for all of the addresses Add (1), Add (2), .. . , Add (m−1) and Add (m), all the address data are accessed, wherebythe error correction information is written into the error correctionmemory bit 12 a.

FIG. 6 shows a storage state of the memory core after completion ofwriting of the error correction information into the error correctionmemory bit.

Error correction information of whether or not an error correction isperformed is stored at every combination of the 64 data bits and 7parity bits which are required to construct the ECC code capable of1-bit error correction. When the error correction is performed, “1” isstored in the error correction memory bit, and when the error correctionis not performed, “0” is stored in the error correction memory bit.

Next, operations at the time of counting the number of error correctionsare described.

FIG. 7 is a timing chart showing a state of read-out of an errorcorrection memory bit and a state of counting of the number of errorcorrections.

For example, when the count start signal is inputted into the counter 15b, all of the addresses Add (0) to Add (m) are continuously selected forthe read-out operation. As a result, data of the error correction memorybit 12 a are read out inside the memory core (not shown). The counter 15b counts up only when the datum of the error correction memory bit 12 ais stored using “1” which means that the error correction is performed.FIG. 7 shows that as a result of the counting, the number of errors is5807 (16AF in a hexadecimal number). The count result is outputtedthrough the output circuit 18.

In a normal test pattern, each access to all the address data isrepeated two or more times. Therefore, when the number of errorcorrections is directly counted by the counter 15 b, the same address iscarelessly counted two or more times. As a result, there arises aproblem that the correct number of error corrections cannot be grasped.However, in the semiconductor memory device 10 d of the fourthembodiment, the error correction memory bit 12 a is used. Therefore,even if the error correction in the same address is performed two ormore times, “1” is just overwritten into the error correction memorybit. Accordingly, when counting up this number, the correct number oferror corrections can be counted.

Next, a semiconductor memory device of a fifth embodiment is described.

FIG. 8 shows a configuration of the semiconductor memory device of thefifth embodiment.

In the diagram, the same elements as those in the semiconductor memorydevices 10 a, 10 b, 10 c and 10 d of the first to fourth embodiments areindicated by the same reference numerals as in the devices 10 a, 10 b,10 c and 10 d and the description is omitted.

The semiconductor memory device 10 e of the fifth embodiment has aconfiguration that the upper limit setting register 16 a and comparisoncircuit 17 shown in the semiconductor memory device 10 a of the firstembodiment are added to the semiconductor memory device 10 d of thefourth embodiment.

According to the configuration as described above, the upper limit setin the register 16 a can be arbitrarily reset in response to the countresult of the correct number of error corrections.

In addition, the semiconductor memory device 10 e of the fifthembodiment may be further configured as follows. The count value memorysignal as shown in FIG. 2 is allowed to be inputted into the register 16a. When the signal goes to a high level, the register 16 a stores thecount result by the counter 15 a instead of externally fetching thesetting upper limit. As a result, deterioration with time can be morecorrectly grasped.

According to the present invention, the upper limit of the number oferror corrections can be changed in response to the upper limit settingsignal inputted externally. Therefore, the upper limit of the number oferror corrections can be arbitrarily set, for example, in response tothe number of error corrections during the test operation.

Further, when the upper limit setting signal is inputted externally, thecount result of the number of error corrections in the counter is set asthe upper limit of the number of error corrections. Then, the upperlimit and the count result after passing of a predetermined time arecompared. Therefore, deterioration with time of the memory cell can begrasped.

Further, after completion of the counting of the number of errorcorrections, when the upper limit setting signal is inputted externally,the upper limit is incremented or decremented in synchronization withthe clock signal. Then, the count result and the upper limit arecompared. Therefore, details of the number of error corrections can begrasped by a signal from the comparator.

Further, an error correction storage section is provided in which theerror correction information of whether or not an error correction isperformed is stored at every combination of the data bits and paritybits required to construct a code capable of 1-bit error correction.Therefore, there can be solved a problem that at the time of countingthe number of error corrections, the error correction in the sameaddress is performed two or more times, so that the correct number oferror corrections cannot be grasped, depending on the test pattern.

The foregoing is considered as illustrative only of the principles ofthe present invention. Further, since numerous modifications and changeswill readily occur to those skilled in the art, it is not desired tolimit the invention to the exact construction and applications shown anddescribed, and accordingly, all suitable modifications and equivalentsmay be regarded as falling within the scope of the invention in theappended claims and their equivalents.

1. A semiconductor memory device having an error correction function ofcorrecting a defective bit, comprising: a counter that counts the numberof error corrections; an upper limit setting section that, when an upperlimit setting signal is inputted externally, sets a count result of thenumber of error corrections in the counter as an upper limit of thenumber of error corrections; and a comparator that compares the upperlimit with the count result in the counter after the passing of apredetermined time.
 2. A semiconductor memory device having an errorcorrection function of correcting a defective bit, comprising: a counterthat counts the number of error corrections; an upper limit settingsection that stores an upper limit of the number of error correctionsand that, when an upper limit setting signal is externally inputtedafter completion of the counting in the counter, increments ordecrements the upper limit in synchronization with a clock signal; and acomparator that compares the count result in the counter with the upperlimit.
 3. A semiconductor memory device having an error correctionfunction of correcting a defective bit, comprising: an error correctionmemory section that stores error correction information of whether ornot the error correction is performed, at every combination of data bitsand parity bits required to construct a code capable of 1-bit errorcorrection.
 4. The semiconductor memory device according to claim 3,wherein the error correction memory section is a surplus sectionresulting from allocating a memory cell array configured by a 4-bit or8-bit unit to data bits and parity bits required to construct the codecapable of 1-bit error correction.
 5. The semiconductor memory deviceaccording to claim 3, further comprising: a counter that counts thenumber of error corrections based on the error correction information.